1. Field of the Invention
Embodiments of the invention relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for patterning a substrate and for implanting into a substrate for manufacturing a device.
2. Discussion of Related Art
Optical lithography is often used in manufacturing electronic devices. It is a process by which a substrate is patterned so that circuit may be formed on the substrate according to the pattern. Referring to FIG. 1a-1e, there are shown simplified illustrations of the optical lithographic process. Generally, the substrate 112 is coated with photo-curable, polymeric photoresist 114 (FIG. 1a). Thereafter, a mask 142 having a desired aperture pattern is disposed between the substrate 114 and a light source (not shown). The light 10 from the light source is illuminated onto the substrate 112 via the aperture of the mask 142, and the light transmitted through the mask's aperture (or the image of the pattern) is projected onto the photoresist 114. A portion of the photoresist 114a is exposed to the light 10 and cured, whereas the rest of the photoresist 114b remains uncured (FIG. 1b). As a result, an image of the mask's apertures may form by the cured portion of the photoresist 114a. 
As illustrated in FIG. 1c, the uncured portion of the photoresist 114b is stripped, and 3D photoresist feature or relief 114a corresponding to the mask's aperture pattern may remain on the substrate 112. Thereafter, the substrate is etched, and trenches 116 corresponding to the negative image of the mask's aperture pattern may form (FIG. 1d). After the remaining photoresist 114b is removed, a patterned substrate 112 may form (FIG. 1e). If a metallic layer is deposited on the trenches, a circuit having a desired pattern may be formed on the substrate 112.
Referring to FIG. 2, there is shown a conventional optical lithographic system 200 for projecting the image of the mask's aperture pattern to the substrate. The optical lithography system 200 comprises a light source 222, an optical integrator 232, and a condenser lens 236. In addition, the optical lithography system 200 may comprise mask 142 having a desired aperture pattern and a projection lens 252. As illustrated in the figure, light having desired wavelength is emitted from the light source 222 to the optical integrator 232 and the condenser lens 234, which are collectively known as an illuminator 230. In the illuminator 230, the light 10 is expanded, homogenized, condensed, or otherwise conditioned. The light 10 is then illuminated onto the mask 142 having the desired aperture pattern to be projected onto the substrate 112. The light 10 transmitted through the apertures of the mask 142 may contain the information on the mask's aperture pattern. The light 10 is then captured by the projection lens 252 which projects the light 10 or the image of the mask's aperture pattern onto the photoresist deposited on the substrate 112. In projecting the image, the projection lens 10 may reduce the image by a factor of four or five.
To generate circuit patterns with smaller feature size (e.g. width of the trench), several modifications have been implemented into the process. As known in the art, the ability to project a clear image of a small feature may depend on, among others, the wavelength of the light used in the process. Currently, UV light with wavelengths of 365 nm and 248 nm, and 193 nm are used. In particular, to generate circuits with 13.5 nm width, argon fluoride (ArF) excimer laser with 193 nm have been proposed.
Although optical lithography is an efficient process with high throughput, the process is not without disadvantages. One disadvantage may include line width roughness (LWR) or line edge roughness (LER). As known in the art, LWR is excessive variations in the width of the photoresist feature formed after uncured portion of the photoresist 114b is stripped from the substrate. If the variations occur on the side surface of the photoresist relief or feature, the variations is known as LER. The roughness or variations due to LWR or LER may be disadvantageous as the variation may be transferred onto the trenches during etch and ultimately to the circuit. The variations become more significant with decrease in feature size of the photoresist relief or trenches. For example, variations of 4 nm or larger have been observed a 193 nm based lithographic process producing 13.5 nm feature size. Because the geometrical shape of a patterned resist feature, including line roughness effects, such as LWR and LER, is transferred from a resist layer to an underlying permanent layer of a device during patterning of the underlying layer, LWR and LER can limit the ability to form devices of acceptable quality for dimensions below about 100 nm. Such variations may lead to non-uniform circuits and ultimately device degradation or failure. In addition, depending on design criteria, device performance may be impacted more by either one of short, medium, or long range roughness.
Several approaches have been attempted to address LWR and LER effects. In one example, dry chemical etch process has been employed which has the ability to remove resist, but generally suffer from pattern dependent loading effects in which the removal is different in densely patterned regions as opposed to isolated features. Such dry chemical etching processes may also impart unwanted defects into a resist pattern, which could result in yield loss. In addition, it is important that any process used to address LWR/LER effects in resist, leave the original resist attributes, such as resist height, width, and profile, intact, in order to maintain tight control of the critical dimension (CD) of underlying features to be patterned.
Another approach used to address LWR and LER effects has been to use deep ultraviolet (DUV) curing by exposing a rough pattern to a UV lamp in which heating through radiation exposure is used to smooth out rough lines. This approach has the unwanted side effect of causing pattern pullback at line segment corners, causing lines to deform in such a way as to render devices useless.
In order to address the diffraction limit of UV lithography processing of resist, where lines or other patterns may have CD feature sizes below the diffraction limit of the illuminating radiation, double patterning lithography (DPL) has been developed. Multiple approaches have been employed in an attempt to ensure success of DPL, including self aligned double patterning lithography and chemical freeze lithography. However, each of these processes may have both advantages and disadvantages with respect to cost and/or yield.
In addition to the aforementioned challenges regarding control of resist patterning, control of the size and shape of patterned substrate features after their formation remains a challenge. It is well known that controlling the etching conditions for patterning substrate features used to form devices, such as polysilicon or metal gates, or silicon fins, may be critical in defining the eventual shape and size of such features after etching. In addition, processing steps such as ion implantation may affect the shape and size of such substrate features, especially those having dimensions on the order of 100 nm or less. For example, ion implantation of substrates to provide doping of devices having silicon fins may inadvertently cause etching/sputtering of the fins. In some cases, the silicon fins may develop pronounced faceting, which may substantially alter device properties of fin-based devices to be formed.
In view of the above, it will be appreciated that there is a need to improve processes that affect device feature patterning, such as resist lithography processes and device doping processes, especially for technologies requiring very small feature sizes, such as sub-100 nm CD devices.